1. Technical Field
The present invention generally relates to a semiconductor memory device and method of operating the same, more particularly relates to a semiconductor memory device for performing a soft program operation after an erase operation is performed and method of operating the same.
2. Related Art
A semiconductor memory device is a memory device for enabling to store and read data. The semiconductor memory device is divided into a random access memory RAM and a read only memory ROM. Data stored in the RAM becomes lost if power is not supplied. This memory is referred to as a volatile memory. However, data stored in ROM is not lost though the power is not supplied. This memory is referred to as non-volatile memory.
A memory cell is programmed though an FN tunneling method when a program operation of the semiconductor memory device is performed. In case that high voltage is applied to a control gate of the memory cell in the program operation, electrons are charged in a floating gate of the memory cell. In a read operation of the semiconductor memory device, threshold voltage of the memory cell varied according to amount of the electrons charged in the floating gate is detected, and read data is determined according to level of the detected threshold voltage.
An erase operation of the semiconductor memory cell may be performed in the unit of selected block. For example, the erase operation may be performed by applying a ground voltage, e.g. 0V to every word line included in the selected block and providing an erase voltage, e.g. 20V to a well of the block.
Since threshold voltage distribution of memory cells of which an erase operation is finished is generally wide, a time taken for the program operation performed after the erase operation may increase. For example, in case that a memory cell having lowest threshold voltage and a memory cell having greatest threshold voltage of the erased memory cells are programmed simultaneously, velocity difference of the program operation between two memory cells occurs.
To improve the velocity difference, a soft program operation is performed after the erase operation is finished.
FIG. 1 is a view illustrating circuit diagram of a string in a memory cell array of a semiconductor memory device.
FIG. 2 is a view illustrating a graph showing threshold voltage (i.e., Vt) distribution according to a conventional soft program operation (i.e., No).
In FIG. 1 and FIG. 2, in the soft program operation, a ground voltage is applied to bit lines BL, and a supply voltage is provided to a drain select line DSL and a ground voltage is applied to a source select line SSL under the condition that a source line SL may be connected to the supply voltage. Every memory cell MC0 to MCn are soft-programmed simultaneously by applying simultaneously a soft program voltage to word lines WL<0:n> so as to have one or more memory cells having threshold voltages higher than a soft program verification voltage SEV. That is, the soft program operation is performed by using a program operation through the FN tunneling method similar to common program operation method (i.e., FN PGM). However, in case that every memory cell is simultaneously programmed through FN tunneling method, threshold voltage of every memory cell increases, and so effect of reducing width of the threshold voltage distribution is inadequate. In other words, the threshold voltage distribution B of the memory cells for which the soft program operation is finished increases comparing to threshold voltage distribution A (where the target threshold voltage is indicated by HEV) of the memory cells before the soft program operation is not performed, but the width of the threshold voltage distribution does not reduce.